رجیستر 8 بیتی
در این برنامه یک رجیستر 8 بیتی با خروجی Seven_Segment طراحی شده است
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity source is
Port ( load : in STD_LOGIC;
clk1 : in STD_LOGIC;
clk2 : in STD_LOGIC;
y : out STD_LOGIC_VECTOR (13 downto 0);
a : in STD_LOGIC_VECTOR (7 downto 0));
end source;
architecture Behavioral of source is
signal tm:STD_LOGIC_VECTOR (7 downto 0);
signal t:STD_LOGIC_VECTOR (13 downto 0);
signal clk:STD_LOGIC;
begin
process(clk1, clk2)
begin
if clk2 = '0' and clk2'event then
clk <= clk1;
end if;
end process;
process (clk,load)
begin
if (clk = '1' and clk'event) then
if load = '1' then
tm <=a;
end if;
end if;
end process;
with tm select
t <= "00000000111111" when "00000000",
"00000000000110" when "00000001",
"00000001011011" when "00000010",
"00000001001111" when "00000011",
"00000001100110" when "00000100",
"00000001101101" when "00000101",
"00000001111101" when "00000110",
"00000000000111" when "00000111",
"00000001111111" when "00001000",
"00000001101111" when "00001001",
"00001100111111" when "00001010",
"00001100000110" when "00001011",
"00001101011011" when "00001100",
"00001101001111" when "00001101",
"00001101100110" when "00001110",
"00001101101101" when others;
y <= not t;
end Behavioral;
