طراحی واحد محاسبات و منطق

ALU  یکی از مهم ترین قسمت های یک  CPU است که از دو بخش

واحد محاسبات: نظیر جمع، تفریق، ضرب و تقسیم و ...

و واحد منطقی: نظیر AND ، OR، XOR و ...

تشکیل شده است.

برنامه ی ذیل برخی از اعمال ذکر شده را انجام می دهد:

 

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity ALU is

    Port ( A : in  STD_LOGIC_VECTOR (3 downto 0);

              B : in  STD_LOGIC_VECTOR (3 downto 0);

              opcode : in  STD_LOGIC_VECTOR (3 downto 0);

              y : out  STD_LOGIC_VECTOR (3 downto 0);

              carry : out  STD_LOGIC;

              overflow : out  STD_LOGIC;

              sign : out  STD_LOGIC;

              zero : out  STD_LOGIC;

              epb : out  STD_LOGIC);

end ALU;

 

architecture Behavioral of ALU is

signal t : STD_LOGIC_VECTOR (4 downto 0);

begin

            with opcode select

                        t <= ('0' & A(3 downto 0)) + ('0' & B(3 downto 0)) when "0000",--sum

                        ('0' & A(3 downto 0)) - ('0' & B(3 downto 0)) when "0001",--sub

                        '0' & A(3 downto 0) + "00001" when "0100",--increment

                        '0' & A(3 downto 0) - "00001"  when "0101",--decrement

                        '0'& A(2) & A(1) & A(0) & '0' when "0110",--left logical shift

                        '0' & '0' & A(3) & A(2) & A(1) when "0111",--right logical shift

                        '0'& A(2) & A(1) & A(0) & A(3) when "1000",--left rotate shift

                        '0'& A(0) & A(3) & A(2) & A(1) when "1001",--right rotate shift

                        '0'& A(2) & A(1) & A(0) & '0' when "1010",--left arithmetic shift

                        '0'& A(3) & A(3) & A(2) & A(1) when "1011",--right arithmetic shift

                        '0' & A(3 downto 0) or '0' & B(3 downto 0) when "1100",

                        '0' & A(3 downto 0) and '0' & B(3 downto 0) when "1101",

                        '0' & A(3 downto 0) xor '0' & B(3 downto 0) when "1110",

                        '0' & A(3 downto 0) nand '0' & B(3 downto 0) when others;

            carry <= not t(4);

            y <= not t(3 downto 0);

            zero <= (t(3) or t(2)or t(1) or t(0));

            sign <= not t(3);

            epb <= not(t(3) xor t(2) xor t(1) xor t(0));

overflow <= not((not A(3) and not B(3) and t(3)) or (A(3) and B(3) and not t(3)) or (not A(3) and B(3) and t(3)) or (A(3) and not B(3) and not t(3)));

end Behavioral;